1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the present invention is in the field of fabrication of electrostatic discharge (“ESD”) protection devices for integrated circuits.
2. Related Art
Continued advances in semiconductor technology have resulted in integrated circuits (“IC”) with smaller and smaller geometries. As the devices become more miniaturized, however, they become more susceptible to electrostatic discharge (“ESD”) damages. By way of background, ESD is a relatively rapid, high-current event resulting from high voltage created when electrostatic charges are rapidly transferred between bodies at different electrical potentials. If not properly contained, ESD discharge can lead to either a reduction in IC performance, e.g. increased leakage current on one or more pins of the IC, or total circuit failure. Consequently, ESD discharge can result in an undesirable increase in the overall manufacturing cost of IC chips.
In an attempt to minimize the effect of ESD discharge, semiconductor manufacturers have fabricated protection devices for the input and output (“I/O”) pads of ICs to absorb the sudden surge of ESD discharge. In one conventional approach, snapback devices, such as open-base NPN transistors, are utilized to provide ESD protection to the I/O pads of ICs. While snapback devices offer ESD protection, they also add undesirable capacitive loads to the I/O pads.
To reduce the capacitive load cause by snapback devices, semiconductor manufacturers employ reverse-biased substrate diodes connected between the I/O pad and the substrate and reverse-biased N-well diodes connected between the Vcc bus and the I/O pad. The substrate diodes protect against a negative ESD discharge by providing a low resistance current path to the substrate to dissipate the negative electrostatic charge, and the N-well diodes protect against a positive ESD discharge by providing a low resistance current path to the Vcc bus to dissipate the positive electrostatic charge. However, the Vcc bus cannot effectively dissipate the positive electrostatic charge. As a result, a Vcc to ground clamp is required to provide a low resistance current shunt path to ground to dissipate the positive electrostatic charge.
One approach utilizes a threshold clamp to provide a current shunt path from the Vcc bus to ground to dissipate the positive electrostatic charge on the Vcc bus. The threshold clamp is activated and starts conducting current when the positive electrostatic charge on the Vcc bus exceeds a threshold voltage, which is typically approximately 7.0 volts. However, a 7.0 volt trigger voltage may be undesirably high for some circuits and, as a result, those circuits can be damaged by the positive electrostatic charge before the threshold clamp turns on and begins shunting current to ground. Also, if the power supply voltage on the Vcc bus exceeds a normal level, the threshold clamp may turn on or partially turn on, resulting in an undesirable current leak through the threshold clamp.
Another approach utilizes a transient clamp to provide a current shunt path from the Vcc bus to ground. The transient clamp turns on and begins conducting at a lower voltage than the threshold clamp, and thus provides a more effective current shunt path than the threshold clamp. The transient clamp utilizes an NFET (N-channel Field Effect Transistor) to shunt current from the Vcc bus to ground. However the NFET consumes a large area in the IC chip and has a low current rating. An example of the above transient clamp is disclosed in U.S. Pat. No. 5,440,162, issued on Aug. 8, 1995, titled “ESD Protection for Submicron CMOS Circuits.”
Thus, there is thus a need in the art for an improved ESD bus clamp. In particular, there is a need in the art for an improved ESD bus clamp having a high current rating, a small size, and a sufficiently low trigger voltage.